Made for your model
Your model, your chip.
Your model, your chip. The same cores and routes, redefined around your model, power budget and volume.
Made for your model
The three production chips came off this same line. Change the model and the power budget, and you get another chip.
Scope
- Routes
- MaskROM · SRAM CIM · near-memory
- Inference cores
- FS-Fusion / Attention / MoE / Linear
- Vehicle
- Fanshi ASIC, or integrated into your SoC
- Delivery
- FPGA sample → tape-out → production
- Process
- SMIC 28 nm
- First step
- Run the model on the FPGA evaluation board
- Package / interfaces
- Per project
Who it is for
- Frozen models shipping at volume
- Industry devices that need their own chip
- Teams with their own SoC adding LLM capability
From an email to a chip
01
Choose the route
Target model, performance and power goals, update cadence, interfaces. The first question is always: how often does the model change?
02
FPGA evaluation
Deploy the inference core on the evaluation board, run the model, measure accuracy and throughput: the first engineering sample.
03
System design-in
Interfaces, system software and field validation around the evaluation results, turning the sample into a product prototype.
04
ASIC delivery
Once the model is frozen: production ASIC, or the IP integrated into your own silicon.
Start from your model
Send the target model, performance and power goals, volume and timeline. We reply with a route recommendation and an evaluation plan.