Move less. Keep inference on the device.
Fanshi organises its technology around where model weights are stored and computed: MaskROM, SRAM CIM and near-memory compute.
Cast the whole model into a single chip.
GPUs and NPUs spend most of their time and power shuttling weights between memory and compute. Fanshi turns that around: weights live in the memory array, and the math happens where they are.
让权重成为硅片的结构。
每 token 外部权重搬运
0MB
运行时保留
就地计算 · 无外部权重搬运
0.8B · INT8 估算，非整机功耗存算分离
权重每个 token 都要搬一遍
传统 NPU / GPU 里，存储和计算是两块硅。生成每一个 token，全部权重都要经过总线走一遍：带宽就是上限，能耗大多花在路上。
存算一体
把权重放进存储阵列
燔石把乘加电路做进存储阵列旁边：权重住在阵列里，激活流过去，结果流出来。总线上不再有权重。
MaskROM
流片时铸进硅片，运行时不再搬运
掩膜存算一体在流片环节把权重物理写入通孔阵列。芯片出厂时模型已经在里面，功耗与单次推理的边际成本降到最低。
One goal, three routes.
All three move weights less, or not at all. They differ in where the weights live and whether the model can still change. The first question to answer: how often does your model change?
- Where weights live
- Mask layer, cast at tape-out
- Runtime movement
- None
- Model updates
- Fixed at tape-out
- Best for
- Stable models, high volume, lowest power and marginal cost
- Where weights live
- Inside the SRAM array
- Runtime movement
- MAC inside the array
- Model updates
- Loaded at boot, updatable
- Best for
- Mid-size models, devices that need field updates
- Where weights live
- High-bandwidth external memory
- Runtime movement
- On-chip streaming
- Model updates
- Continuous iteration
- Best for
- Large, fast-evolving models in heavy-load nodes
On-device decode speed
Forge design target, Qwen 3.5 0.8B
System power
Forge lightweight edge class
Data stays on device
Local inference, no network required
Marginal cost per inference
After a one-time chip purchase
Choose the route for your project
Send the target model, performance and power goals and update cadence. We reply with a route and an evaluation plan.