Multimodal fusion inference IP
FS-FusionJoint vision-language understanding (VLM) and multi-sensor fusion, computed in place at the edge.
Native SmolVLM + SegFormer MiT fusion pipeline
License the inference core into your own silicon.
License Fanshi inference cores into your own ASIC or FPGA. One core family, four architectures, running on an evaluation board first.
Hybrid attention inference IP
FS-AttentionNative support for hybrid-attention large language models.
Qwen3 / 3.5 (0.6B to 9B) and SmolLM2
Sparse mixture-of-experts inference IP
FS-MoEBuilt for dynamically activated sparse models, carrying large parameter counts within limited bandwidth.
Large sparse models on edge budgets
Linear attention and new-architecture IP
FS-LinearLinear attention and RNN-style architectures such as DeltaNet.
Very low latency streaming with unbounded context
Run it on an FPGA first. Decide on tape-out later.
The evaluation board plus customizable IP licensing validates model mapping, interfaces and the full system path, so an engineering sample exists before silicon does.
From IP licence to tape-out
01
Choose the route
Target model, performance and power goals, update cadence, interfaces. The first question is always: how often does the model change?
02
FPGA evaluation
Deploy the inference core on the evaluation board, run the model, measure accuracy and throughput: the first engineering sample.
03
System design-in
Interfaces, system software and field validation around the evaluation results, turning the sample into a product prototype.
04
ASIC delivery
Once the model is frozen: production ASIC, or the IP integrated into your own silicon.
Ask about IP licensing
Tell us the target device, model and interfaces. We reply with IP coverage and an evaluation plan.