Questions about the chips, the IP and validation.

ASIC chips for edge LLM inference (Forge, Trident, Argus), FPGA evaluation boards, and inference core IP (FS-Fusion, FS-Attention, FS-MoE, FS-Linear) that can be deployed into a customer ASIC or FPGA.

Compute-in-memory performs multiply-accumulate inside the memory array, so weights never leave the storage cells. Near-memory compute places compute units next to high-bandwidth memory and uses on-chip streaming to minimise data movement. The first gives the lowest power and marginal cost; the second suits models that keep evolving.

Not on the MaskROM route: weights are fixed at tape-out. SRAM compute-in-memory loads weights at boot and can be updated. Near-memory compute keeps weights in external memory and supports continuous iteration.

Forge targets Qwen 3.5 0.8B; Trident supports up to Qwen 3.5 35B; Argus runs SmolVLM, SegFormer and similar vision models. The IP family covers Qwen3 / 3.5 (0.6B to 9B), SmolLM2, sparse MoE models and DeltaNet-style linear attention.

They are decode-throughput design targets for the core model listed with each product. Exact model, precision, batch size and test platform are confirmed per project. The live demo on the site shows the measured decode rate of that conversation.

Yes. All four cores target both ASIC tape-out and FPGA prototyping, with an evaluation board for early validation, so an engineering sample can exist before silicon.

A mature domestic SMIC 28 nm supply chain. The gains come from architecture, not from advanced nodes, which keeps cost and supply predictable.

Email info@fanshi-silicon.com with the target model, performance goal, power budget, interfaces and project timeline.